Freescale Semiconductor /MKW20Z4 /XCVR /TSM_TIMING00

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TSM_TIMING00

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PLL_REG_EN_TX_HI0PLL_REG_EN_TX_LO0PLL_REG_EN_RX_HI0PLL_REG_EN_RX_LO

Description

TSM_TIMING00

Fields

PLL_REG_EN_TX_HI

Assertion time setting for PLL_REG_EN TX sequence.

PLL_REG_EN_TX_LO

Deassertion time setting for PLL_REG_EN signal or group TX sequence.

PLL_REG_EN_RX_HI

Assertion time setting for PLL_REG_EN signal or group RX sequence.

PLL_REG_EN_RX_LO

Deassertion time setting for PLL_REG_EN signal or group RX sequence.

Links

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